1. Field of the Invention
The present invention relates generally to high speed memory devices, and more specifically, to techniques for initializing and calibrating controllers in high speed memory devices.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In today's complex computer systems, speed, flexibility, and reliability in timing control are issues typically considered by design engineers tasked with meeting customer requirements while implementing innovations which are constantly being developed for the computer systems and their components. Computer systems typically include a memory sub-system which includes a memory array and one or more memory controllers which provide access to the memory array. The memory array generally includes a plurality of memory devices which may be used to store programs and data and may be accessible to other system components such as processors or peripheral devices through the memory controller. Typically, memory devices are grouped together to form memory modules, such as dual-inline memory modules (DIMMs). Computer systems may incorporate numerous modules to increase the storage capacity in the system.
Each read request to the memory array has an associated read latency period corresponding to the interval of time between the initiation of a read request from a requesting device, such as a processor, and the time the requested data is delivered to the requesting device. Similarly, for each write request to the memory array, there is a write latency corresponding to the time it takes from the initiation of a write request to be initiated by a requesting device and the data to be written to the memory. A memory controller may be tasked with coordinating the exchange of requests and data in the system between requesting devices and each memory device such that timing parameters, such as latency, are considered to ensure that requests and data are not corrupted by overlapping requests and information.
During initialization of the memory sub-system, latency periods are set to insure proper communication and data exchange between the memory array and the memory controller. During initialization, alignment of read data access in accordance with read latency, as well as alignment of write data access in accordance with write latency is set (i.e., the sub-system is calibrated). Calibrating the memory sub-system upon initialization or system reset introduces a number of design challenges. To test and calibrate the memory controller to ensure proper data exchange, test patterns are often generated and sent to and from the memory array through the array controller. Often, these test patterns are provided by components external to the memory sub-system. However, the external transmission of data patterns may be disadvantageous in certain applications.
The present invention may address one or more of the concerns set forth above.